Concurrent statements in VHDL used in the dataflow model are executed concurrently. Hence, the ordering of these statements does not affect the resulting output.
Concurrent Signal Assignment
- The concurrent signal assignment statement assigns a value or the result of evaluating an expression to a signal.
- This statement is executed whenever a signal in its expression changes value. However, the actual assignment of the value to the signal takes place after a certain delay and not instantaneously as for variable assignments.
- The expression can be any logical or arithmetical expressions.
Syntax
signal <= expression;
Example
y <= ‘1’;
z <= y AND (NOT x);
A vector with all bits having the same value can be obtained using the OTHERS keyword as shown here.
SIGNAL x: STD_LOGIC_VECTOR(7 DOWNTO 0);
x <= (OTHERS => ‘0’); — 8-bit vector of 0, same as “00000000”
- Many of these statements can be active at the same time. The VHDL simulator monitors the RHS of each concurrent statement and any time a signal changes, the expression on the RHS is immediately evaluated.
- The new value is assigned to the signal on the left hand side after an appropriate delay.
Concurrent construct has different types of statements.
- With – select statement
- When – else statement
- Generate statements
- Block statement.
With Select Statement (Selected Signal Assignment)
Syntax
With expression Select
target-signal < = exp-1 when choice1
exp-2 when choice2|choice3
.
.
.
exp-n when choice
exp-m WHEN OTHERS;
- In the above syntax, if expression is equal to choice1, then exp-1 is assigned to signal. Otherwise, if expression is equal to choice2 or choice3, then exp-2 is assigned to signal.
- If expression does not match any of the above choices, then exp-m in the optional WHEN OTHERS clause is assigned to signal.
- ‘With Select’ statement evaluates expression and compares that value to each choice
- The matching choice value has its expression assigned to target in ‘When’ statement
- Each value in the range of the expression type must be covered by one
e.g. 4 : 1 multiplexer using with-select statement.
Library IEE;
Use IEEE.std_logic_1164.all;
entity MUX is
port (I : in bit_vector (3 downto 0);
S : in bit_vector (1 downto 0);
Y : out bit);
end MUX;
architecture MUX_41 of MUX is begin
With S Select
Y < = I(0) when “00”
I(1) when “01”
I(2) when “10”
I(3) when “11”,
‘0’ when others; — optional
end MUX_41;
Bit vector I has four signal components I(0), I(1), I(2), I(3).
When-Else Statement (Conditional Signal Assignment)
The conditional signal assignment statement selects one of several different values to assign to a signal based on different conditions. This statement is executed whenever a signal in any one of the value or condition changes.
Syntax
target < = exp-1 when condition-1 else
exp-2 when condition-2 else
…
exp-n when condition;
Example
z <= in0 WHEN sel = “00” ELSE
in1 WHEN sel = “01” ELSE
in2 WHEN sel = “10” ELSE
in3;
The conditional signal assignment statement selects different values for the target signal based on the specified, possibly different conditions.
Library IEE;
Use IEEE.std_logic_1164.all;
entity MUX is
port (I: in bit vector (3 downto 0); S: in bit_vector (1 downto 0); Y : out bit);
end MUX;
architecture MUX_41 of MUX is begin
Y<= I(0) when S<= ”00” else
I(1) when S<= ”01” else
I(2) when S<= ”10” else
I(3) when S<= ”11” else
‘0’;
end MUX_41;
Generate Statements
- The generate statements are concurrent statements with embedded internal concurrent statements, which can be interpreted as a circuit part.
- There are two types of generate statements.
- The first type is the for generate statement, which is used to create a circuit by replicating the hardware part.
- The second type is the conditional or if generate statement, which is used to specify whether or not to create an optional hardware part.
- The generate statements are especially useful for the parameterized design.
- The generate statement is interpreted during explanation, and therefore, has no simulation semantics associated with it. It resembles a macro expansion.
The generate statement provides for a compact description of regular structures such as memories, registers, and counters.
For Generate Statement
Adder4 IS PORT ( Cin: IN STD_LOGIC;
A, B: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Cout: OUT STD_LOGIC;
SUM: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END Adder4;
ARCHITECTURE Structural OF Adder4 IS
COMPONENT FA PORT ( ci, xi, yi: IN STD_LOGIC;
co, si: OUT STD_LOGIC);
END COMPONENT;
SIGNAL Carryv: STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
Carryv(0) <= Cin;
Adder: FOR k IN 3 DOWNTO 0 GENERATE
FullAdder: FA PORT MAP (Carryv(k), A(k), B(k), Carryv(k+1), SUM(k));
END GENERATE Adder;
Cout <= Carryv(4);
END Structural;
Conditional Generate Statement
Syntax
gen-label :
if boolean-exp generate
end generate ;
concurrent statements ;
A simpler example is when a buffer is to be selected that has different delays based on the value of a constant. Here are the generate statements for such an example.
Example
GA: if USER_WANTS = LOW_DELAY generate
Z <= A after 2 ns;
end generate;
GB: if USER_WANTS = MEDIUM_DELAY generate
Z <= A after 10 ns;
end generate;
GC: if USER_WANTS = HIGH_DEU\Y generate
Z <= A after 25 ns;
end generate;
- The if-generate statement is also useful in modeling repetitive structures, especially in modeling boundary conditions. An if-generate statement does not have an else or an else-if branch.
- We can use generate statement in sequential modeling also.
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