Pros and Cons of VHDL

Table of Contents

The Pros and Cons of VHDL are as follows.

The VHDL can be used as a communication medium between different CAD and CAE tools, between chip vendors and CAD tool users.
The language supports hierarchy that is, A digital system can be modelled as a set of interconnected components, each component, in turn, can be modelled interconnected subcomponents each component in turn can be modelled as a set of interconnected subcomponents.
VHDL is not technology – specific, but capable of supporting technology specific features.
It supports both synchronous and asynchronous timing models.
The language is publicly available, human-readable machine readable and above all it is not proprietary.
It is IEE and ANSI standard. Therefore, models described using this language are portable.
It supports three description styles structural, dataflow and behaviour. The design can be expressed in any combination of these three descriptive styles.
Arbitrarily large designs can be modelled using the VHDL and there are no limitations on the size of a design.
Test benches can be written using the same language to test other VHDL models.
Nominal propagation delays, set UP and hold timing, timing constraints and spike detection can also be described very naturally in this language.
VHDL is not a case sensitive language.

Capabilities / Advantages of VHDL

VHDL provides capabilities or advantages of VHDL as described below

It makes it possible to design or verify electronic designs or models without knowing the implementation device/technology (CAD/FPGA etc).
With the electronic design, we can target many device architectures.

This makes it possible to change development tools.
The language can also be used as an exchange medium between chip vendors and CAD tool users.
We can verify the functionality of the same VHDL code by using different software tools such as Xilinx, Actel etc.

It has powerful language constructs due to which we can write code descriptions of complex control logic.
It supports both top-down and bottom-up or mix methodology.
It supports modifiability as the language is easy to read, hierarchical and structured.

Because VHDL is a standard, your design description VHDL for a design can be simulated on different tools, one platform to another.
The Source code of VHDL for a design can be used with any Synthesis tool and the tool and the design can be implemented in any device which is supported by synthesis tool.

If we implement the VHDL tool on a CPLD or FPGA it increases the efficiency of the product to hit the market quickly.
When the production volumes reach above the appropriate level, VHDL facilitate the development of an ASIC.
As the VHDL is a well-defined language, we can be assured. The ASIC vendor will deliver device with the expected functionality.

PLDs and VHDL together facilitate a speeding design process.
VHDL makes it possible to describe out design quickly and correctly and along with programmable logic devices, we can shorten the Non-recurring Engineering (NRE) examples.
Therefore, VHDL and PLDs combined together acts as a powerful vehicle to bring in the market in record time.

The shortcomings or disadvantages of VHDL are as below

Synthesis results of VHDL may vary from one tool to another.
Most synthesis tools allow the designer use synthesis directives to some level of control over implementation to make area efficient version speed efficient implementation choices.
VHDL compilers do not produce optimal implementation, The optimal solution depends on the design objectives.
It has poor implementation due to the results of inefficient code. For example, inefficient C or C++ code results slow execution times or poor memory utilization.
The inefficient VHDL code results in repetitive unneeded and non-optimal logic.
Most synthesis tools allow designers to specify technology specific gate level implementation, but descriptions ‘of these types are neither high-level nor device independent.
For analog electronics, the VHDL is not yet standardized. It is in progress.