This article describes the two kinds of subprograms in VHDL: procedures and functions. A function call can be used within an expression. A procedure call may be a sequential or a concurrent statement. It is possible for two or more subprograms to have the same name. This is called overloading. Subprograms A subprogram defines a […]
Concurrent statements in VHDL used in the dataflow model are executed concurrently. Hence, the ordering of these statements does not affect the resulting output. Concurrent Signal Assignment The concurrent signal assignment statement assigns a value or the result of evaluating an expression to a signal. This statement is executed whenever a signal in its expression
A set of VHDL statements that executes in sequence is called sequential statements in VHDL. Sequential Statements in VHDL The syntax of a sequential signal assignment is identical to that of the simple concurrent signal assignment except that the former is inside a process. Syntax signal-name <= value-expression; Note that the concurrent conditional and selected
FPGA (Field Programmable Gate Array) is a fine grain device with small logic blocks and has medium to very high density suitable for large complex densities. In FPGA, delays are dependent on applications. It uses SRAM or Antifuse technology. It has more density and it is more volatile. Features of FPGA It has high complexity,
Complex Programmable Logic Device (CPLD) is one of the PLD. It is used for the implementation of the logical circuits. Lets see something about Programmable Logic Devices (PLDs) first. Programmable Logic Devices (PLDs) Variety of IC’s can have their logic function programmed into them after they are manufactured. Most of devices use technology that allows
In VHDL, the architecture body of an entity can be expressed in many ways. In this article, Behavioral Style of Modelling in VHDL is explained with example. As specified in previous articles, the internal details of an entity are specified by an architecture body using any of the following modelling styles: As a set
In VHDL, the architecture body of an entity can be expressed in various ways. In this article, data flow style of modelling in VHDL is explained with example. As specified in previous article, the internal details of an entity are specified by an architecture body using any of the following modelling styles: As a
The internal details of an entity are specified by an architecture body using any of the following modelling styles: As a set of interconnected components (to represent structure: Structural Style of Modelling), As a set of concurrent assignment statements (to represent dataflow: Data flow Style of Modelling), As a set of sequential assignment statements (to
In this article, entity and architecture declaration in VHDL are discussed with examples. Let us first learn about some lexical elements used in VHDL. Lexical Elements The lexical elements are the basic units in a VHDL program. comments, identifiers, reserved words, number, characters and strings. Comments The comments are for documentation purpose only. It does
All the objects in VHDL can be declared using type specification. A wide range of data types in VHDL are available. A type declaration statement is TYPE type_name is type_mark; Two main data types in VHDL are Scalar Data Types Composite Data Types Scalar Data Types in VHDL The scalar data types describe objects that
